Integrated circuits are widely used in consumer, commercial and industrial applications. Many integrated circuits utilize large numbers of Field Effect Transistors (FET) to provide integrated circuit functionality. As is well known to those having skill in the art, an FET generally includes spaced apart source and drain regions in an integrated circuit substrate, and an insulated gate on the substrate therebetween.
As the integration density of integrated circuit devices continues to increase, the width of an insulated gate may decrease. This decrease in width may undesirably increase the resistance of the insulated gate. In order to decrease the resistance, it is known to form an insulated gate using a multilayer structure, including a metal layer that can have a small resistance. Accordingly, it is known to provide an insulated gate that comprises a gate oxide on an integrated circuit substrate, a polysilicon pattern including polysilicon sidewalls, on the gate oxide, and a metal pattern on the polysilicon pattern. The gate oxide can comprise silicon oxide, silicon oxynitride and/or other oxides, and may include other materials, as well.
FIGS. 1-3 are cross-sectional views illustrating conventional insulated gates during intermediate fabrication steps thereof. As shown in FIG. 1, an insulated gate 80 includes a gate oxide 20 on an integrated circuit substrate 10, such as a silicon semiconductor substrate, and a gate electrode 45 on the gate oxide 20. The gate electrode includes a polysilicon pattern 30 including polysilicon sidewalls 30a, and a metal pattern 40 on the polysilicon pattern 30. A metal nitride pattern 35 also may be provided between the polysilicon pattern 30 and the metal pattern 40. The metal pattern 40 may comprise tungsten, and the metal nitride layer pattern 35 may comprise tungsten nitride. The gate electrode may be formed by anisotropic etching, to pattern blanket layers that are formed on the substrate 10. As is well known, this etching may damage the polysilicon pattern 30 and/or the substrate 10.
Referring now to FIG. 2, it is known to at least partially cure the etching damage by performing a selective oxidation process, to thermally oxide the sidewalls 30a of the polysilicon pattern after the gate electrode 45 is formed. The selective oxidation process can be carried out under conditions that oxidize the polysilicon pattern 30, but do not oxidize the metal pattern 40 or the metal nitride pattern 35.
Unfortunately, this oxidizing may undesirably increase the thickness of the gate oxide 20. For example, Table 1 shows measured thickness of a gate oxide 20 after a selective oxidation process. In Table 1, the initial thickness of the gate oxide was 50 Å.
TABLE 1thickness of the gate oxide 20 (Å)line width of the gate (80 nm)line width of the gate (200 nm)Tc (center)Te (edge)Tc (center)Te (edge)78874678
As shown in Table 1, for a relatively narrow gate (e.g., 80 nm), the thickness Tc in the center of the gate increased to about 78 Å, and the thickness Te at the edge of the gate increased to about 87 Å. For a wide gate (e.g., about 200 nm), the center thickness Tc did not increase, but the edge thickness Te increased to about 78 Å. These increases in thicknesses may be undesirable, because it may lead to an increased threshold voltage of the field effect transistor.
Moreover, the selective oxidation process may not completely prevent oxidation of the metal pattern 40. In particular, as shown in FIG. 3, crystal growth may occur from a surface of the metal pattern 40 in a subsequent thermal process when part of the metal layer pattern 40 becomes oxidized during the selective oxidation process. This crystal growth may form whiskers 99 that emerge from the metal pattern 40. These whiskers may lead to device failure.